The present invention relates to semiconductor chips, particularly to a high speed level converter to convert a TTL level of an input signal to a CMOS level.
Generally, the level of a TTL signal is defined as a logic low level if it is between 0 V and 0.8 V, while the level is defined as a logic high level if it is between 2.2 V and 5 V. On the other hand, the level of CMOS signal is defined as a logic low level if it is at the VSS level (0 V), while it is defined as the logic high level if it is at the VCC level (5 V). Thus, when the TTL signal is applied as an input signal to CMOS semiconductor chips, a level converter is needed to convert the TTL signal level to the CMOS signal level. A conventional level converter comprising a NOR gate, as shown in FIG. 1, converts the TTL signal level to the CMOS signal level by a voltage pull-up or pull-down operation.
But, if the input level of the TTL signal is 2.2 V, the PMOS pull-up transistor PI2 and the NMOS pull-down transistor NI2 are turned on at the same time, so that the PMOS transistor PI2 must be smaller than that of the NMOS transistor NI2 in order to pull down the output to the low-level, e.g., a zero level. Thus, the converting speed of the NOR gate 1 becomes slow when the TTL signal changes from the high level to the low level since the PMOS transistor PI2 is relatively smaller than the NMOS transistor NI2. This becomes an obstacle to high-speed operation.